Along with electronic products being developed toward having multi-functionality, high performances and high operating speed, semiconductor manufacturers have endeavored to provide a multi-chip module (MCM) for incorporating a plurality of chips in a semiconductor device to meet the above requirements for the electronic products.
U.S. Pat. No. 6,303,997 discloses a semiconductor device integrated with a plurality of chips. Referring to FIG. 1, on an upper surface of a substrate 10 there are provided a semiconductor chip 11 electrically connected to the substrate 10 and a fabricated BGA (ball grid array) semiconductor package 12. During fabrication of the multi-chip semiconductor device, the semiconductor chip 11 is first electrically connected to the upper surface of the substrate 10 via a plurality of bonding wires 111. Subsequently, the fabricated BGA semiconductor package 12 is electrically connected to the substrate 10 via a plurality of solder balls 121.
However, in the foregoing semiconductor device, a plurality of wire-bonding pads and solder-ball pads need to be provided on the substrate for electrically connecting the semiconductor chip and the semiconductor package to the substrate. This not only sets a limitation on the substrate layout but also requires high-density fabrication processes to form the pads, thereby increasing the fabrication cost. Additionally, since the electrical connection between the semiconductor chips in the semiconductor device is established through the bonding wires, the solder balls, and circuits of the substrate, such electrically conductive path is very complex and makes the electrical performances hard to be improved.
U.S. Pat. No. 5,783,870 discloses another semiconductor device incorporated with a plurality of chips, in which a plurality of semiconductor packages are integrated as a single module semiconductor device. Referring to FIG. 2, in this semiconductor device, a second semiconductor package 20b is stacked on a first semiconductor package 20a and is electrically connected to the first semiconductor package 20a by bonding a plurality of solder balls 21 of the second semiconductor package 20b to an upper surface of the first semiconductor package 20a. And a third semiconductor package 20c is stacked on and electrically connected to the second semiconductor package 20b in a similar manner.
However, the foregoing semiconductor device having the plurality of stacked semiconductor packages has significant drawbacks. Only areas aside from a chip attach region on a substrate of the underlying semiconductor package can be used for electrical connection with the solder balls of the overlying semiconductor package. In other words, electrically-connecting areas on the substrate of each of the stacked semiconductor package are restricted, thereby affecting the trace routability of the substrate, and the number and distribution of input/output (I/O) connections of the overlying semiconductor packages are also restricted, making the design flexibility of the entire semiconductor device undesirably reduced. Further, the plurality of semiconductor packages must formed before performing the stacking process, such that the overall fabrication processes are complex and the fabrication time and cost are increased. Moreover, the electrical connection between the semiconductor chips of the stacked semiconductor packages is still achieved via the substrate circuits and the solder balls of each of the semiconductor packages, such electrically conductive path is very complex and makes the electrical performances hard to be improved.
Additionally, since a plurality of semiconductor chips are incorporated in the foregoing multi-chip module (MCM), and electronic elements and circuits on the semiconductor chips are highly integrated, a large amount of heat would be generated by the semiconductor chips during operation. If the heat cannot be effectively dissipated, the performances and lifetime of the semiconductor chips would be reduced.
Furthermore, during general fabrication processes of a semiconductor device, chip carriers should be first fabricated by chip-carrier manufacturers (such as circuit-board manufacturers), and then the chip carriers can be subject to chip-mounting and molding processes by semiconductor packaging manufacturers to eventually form the semiconductor device having electronic performances such as integrated circuit design houses or integrated circuit manufactories. Therefore, such fabrication processes of the semiconductor device, involving different manufacturers such as chip-carrier manufacturers and semiconductor packaging manufacturers, are complicated and usually cause difficulty in interface integration. In case the client intends to alter the functional design of the semiconductor device, it would involve further complex change and interface integration, such that the flexibility in alteration and the economical effects cannot be achieved.
Therefore, the problem to be solved herein is to provide a highly integrated semiconductor device with improved electrical quality, which can be fabricated by simplified processes and at lower cost, and also can solve the problems of heat dissipation, packaging and interface integration.